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september 2 0 13 rev 3 1/15 15 AN2168 application note st10f27x hardware development getting started introduction the st10f27x mcus are derivatives of the stmicroelectronics st10 family of 16-bit cmos microcontrollers. they combine high cpu performance (cpu frequency up to 64 mhz) with high peripheral functionalities and e nhanced i/o-capabilities. they offe r on-chip high speed single voltage flash memory, on-chip high speed ram and support clock generation via pll or an external clock. the st10f27x mcus also provide an enhanced 16-bit dsp co-processor to improve their performance in signal processing algorithms. this application note complements the st10f27x datasheet and user manual by describing the minimum hardware environment required to build an application around the st10f27x. a number of features of the st10f27x devices are described in the first five ch apters. in the sixth, a basic schematic is given illustrating the minimum hardware required to get the st10f27x runn ing. for a deepe r description of these features, refer to the st10f27x datasheet or user manual . in order to build an application around st10f27x, the application board should, at least, provide the following features: power supply clock management reset control boot mode settings www.st.com
AN2168 2/15 contents 1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin vstby / ea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 main clock control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1 direct drive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.2 prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.3 pll operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 32 khz low power oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 how to reset external devices with st10f27x reset signals . . . . . . . . . . . . . . 7 3.2.1 rstout pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.2 bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 start up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 boot management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 single chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 boot from external memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 st10f27x basic schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AN2168 1 power supply 3/15 1 power supply 1.1 overview the st10f27x devices are processed in 0.18 m technology. st10f27x core logic and i/o peripherals need different power supplies. in fact, st10f27x core logic operates with an 1.8v power supply while the i/o peripherals operate with a power supply in the 4.5v to 5.5v range. the st10f27x devices are single supply. this means that just one external supply of 5v is necessary to feed both core and peripherals. the power management block includes a regulator to provide the core logic 1.8v supply from the 5v input supply. the internally generated 1.8v supply is available on pin v18 (pin 56) of the st10f27x. no external supply can be connected to v18 . a decoupling ceramic capacitor of a typical value 10nf(max 100nf) has to be connected between the v18 pin and the nearest vss pin. the main purposes of this capacitor are to: compensate voltage drops due to pulsive current sinked by the device. close the feedback loop of the internal voltage regulator making the system stable. a capacitor of a value 100nf has to be connected for each couple vdd and the nearest pin vss. 1.2 pin v stby / ea on the st10f27x, the pin 99 provides two functionalities: v stby voltage(4.5 - 5.5v) applied on pin 99 maintains the ram powered when st10f27x main power is off. it must be applied be fore switching off the main power supply. ea functionality which configures the st10f27x to start from external memory if its level is low during reset. ta b l e 1 contains the different configurations and the needed hardware for each case (if stand by mode is used or not). table 1. v stby /ea ea = 1 ea = 0 stand by mode used vstby = 5v when vdd is turned off stand by mode not used vstby = 0v vstby ex ea /v stby vss vss ea 4 .. 5.5 v vdd ea /v stby vss ea /v stby
2 clock management AN2168 4/15 2 clock management internal operation of cpu and peripherals are controlled by the same main clock named fcpu. it is provided by the on-chip clock generator. the rtc module can be controlled either by the st10f27x main clock or by th e auxiliary 32 khz oscillator. 2.1 main clock control unit the st10f27x core and peripherals can operate with a frequency up to 64 mhz. the st10f27x main clock can be: generated using the st10f27x inte rnal oscillator amplifier. in th is case, the input signal for the internal oscillator is gener ated by an external crystal or resonator with a frequency between 4mhz and 12 mhz, and is connected between xtal1 and xtal2: xtal1 is the input and xtal2 is the output. this configurat ion is available when using on chip pll or the prescaler operation. forced by an external clock when the direct drive option is selected. in this case, the internal oscillator is disabled and neither the external crystal nor resonator is needed. the external clock is input on the xtal1 pin of the st10f27x and the xtal2 pin must be left unconnected. the clock generation mode is selected during reset according to port 0 lines: p0h.5, p0h.6, p0h.7. each mode is described below. 2.1.1 direct drive operation when pins p0h.7 = 0, p0h.6 = 1, p0h.5 = 1 during reset, the cpu clock is directly driven from the external generator connected to xtal1 pin. in this case, neither the crystal nor the resonator is used. figure 1. st10f27x direct drive 2.1.2 prescaler operation when pins p0h.7 = 0, p0h.6 = 0, p0h.5 = 1 during reset, the cpu clock is derived from the internal oscillator amplifier. the input clock signal is generated by a crystal or a re sonator with a frequency between 4mhz and 8 mhz. the cpu frequency is equal to the input signal on pin xtal1 divided by 2 external clock xtal1 xtal2 unconnected 1 .. 64 mhz st10f27x p0h.5 = 1 vdd p0h.6 = 1 vdd p0h.7 = 0 vss 8 kohms
AN2168 2 clock management 5/15 figure 2. prescaler operation for more details, please refer to the st10f27x datasheet . 2.1.3 pll operation for the remaining combinations of pins p0h.7, p0h.6 and p0h.5, the pll operation is enabled and provides the st10f27x with a main clock. the pll multiplies the input frequency entered on pin xtal1 by a factor selected by the pins p0h.7, p0h.6 and p0h.5 levels. for more details regarding the maximum crysta l frequency and the resulted cpu frequency, refer to st10f27x datasheet . example: if a 5 mhz external crystal is used and p0h[7..5 ] = 101 configuration is selected, st10f27x will run with a 40 mhz frequency. this exampl e is illustrated in the following figure. figure 3. pll operation example 2.2 32 khz low power oscillator when power down mode is entere d, the main oscillator generati ng the st10f27x main clock is switched off. if the rtc module needs to continue running during power down mode, a reference clock is needed. therefore, a 32 khz crystal is connected to the low power oscillator pins xtal3 and xtal4, in order to give a reference clock to the rtc module if the main oscillator is stopped. xtal1 st10f27x xtal2 crystal p0h.6 = 0 vss p0h.5 = 1 vdd p0h.7 = 0 vss xtal1 st10f27x xtal2 crystal p0h.6 = 0 vss p0h.5 = 1 vdd p0h.7 = 1 vdd 5 mhz 1mhoms
2 clock management AN2168 6/15 figure 4. 32 khz oscillator if the 32 khz oscillator is not used, xtal3 must be tied to ground a nd xtal4 must be left unconnected. xtal3 st10f27x xtal4 32 khz crystal for more details concerning capacitance, refer to st10f27x datasheet
AN2168 3 reset management 7/15 3 reset management 3.1 external reset circuitry figure 5 and figure 6 summarize the hardware required to operate a good reset. the first one should be used when the power down mode is not required by the application, whereas the second one shows the hardware configuration in order to use the power down mode. figure 5. external reset circuitry when power down mode is not used figure 6. external reset circuitry when power down mode is used 3.2 how to reset external devi ces with st10f27x reset signals if the application uses the st10f27x with external devices, such as other microcontrollers, and if the external devices should be reset by the st10f27x beyond the st10 reset, there are two ways to do this: using the rstout pin using the bidirectional reset option provided by the st10f27x vdd internal pull-up st10f27x of 50 - 250 kohms gnd rpd internal weak pull down of 200 ua vdd 220k-1m r0 rstin external reset circuitry reset signal open drain output vdd internal pull-up st10f27x of 50 - 250 kohms gnd rpd internal weak pull down of 200 ua vdd 220k-1m r0 rstin external reset circuitry reset signal open drain output gnd 1uf
3 reset management AN2168 8/15 3.2.1 rstout pin rstout signal is used to reset external devices that don?t need initialization before einit instruction of the st10f27x. in this case, the user can execute some code before initializing the external device. the reset circuitry on rstin and rpd pins used in this case is the same circuitry described in the previous section. 3.2.2 bidirectional reset the bidirectional reset changes rstin pin from a pure input to an open drain output with an integrated pull-up resistor. this mode is used: to convert software and watchdog resets into hardware resets to provide a reset signal to external devices that can?t be connected to rstout pin because it?s maintained active during the st10 initialization. pin rstin may be connected to external reset devices with an open drain output driver to avoid conflict. for more details, refer to the st10f27x datasheet in the section for ?bidirectional reset?. rstin used to reset st10f27x rstout used to reset external devices einit
AN2168 4 start up configuration 9/15 4 start up configuration port 0 is used to select the start up system configuration by the mean of external pull down resistors. during reset, port 0 lines are set to input mode with internal pull up resistors. the port 0 pins are read at the end of the reset sequence. the following table summarizes the port0 lines corresponding to the start up features: table 2. port 0 fields note: 1 a low level is applied using a pull down resistor of 8 kohms. for more details regarding the p0 fields and corresponding meanings, refer to st10f27x datasheet or user manual . port 0 lines function comments p0l.0 emulation mode 1) p0l.1 adapt mode 1) p0l.4, p0l.5 boot strap mode 1) see section 5: boot management p0l.6, p0l.7 bustyp: cs0 bus type configuration 1) p0h.0 wrc write/ read configuration 1) p0h.1, p0h.2 cssel: chip select 1) p0h.3, p0h.4 salsel: cs0 address lines 1) p0h.5.. p0h.7 clkcfg: clock configuration 1) see section 2: clock management
5 boot management AN2168 10/15 5 boot management different boot modes are available on st10f27x devices: the bootstrap mode provides a mechanism to load a program in ram of the st10f27x devices without using internal or external memory. the single chip pin ea allows the device to boot either from the internal flash or from an external memory. 5.1 bootstrap loader the st10f276 provi des the following boot capabilities: standard bootstrap: this mode downloads a start up program of 32 bytes through the serial interface or of 128 bytes through the can interface after reset in the st10f276 ram. alternate bootstrap: this mode executes a user bootstrap code written by the customer starting at address 09?0000 if some conditions are met. selective bootstrap: this mode is a sub-case of the alternate bootstrap mode. it?s triggered when the conditions required for the alternate bootstrap are not met. for more details concerning the alternate bootstrap mode, please refer to the st10f276 user manual. the bootstrap mode is selected according to p0l.4 and p0l.5 levels during reset. table 3. st10f27x bootstrap modes example: the following figure illustrates the ha rdware required for th e standard bootstrap loader via can interface. for more details, refer to the st10f27x user manual . p0l.4 p0l.5 bootstrap mode comments 0 1 standard bootstrap use a pull up resistor on p4.5 in order to have a stable level on this pin during bootstrap via can. to avoid high consumption, high resistor values must be chosen. for more details please refer to the st10f27x user manual 00 reserved 1 0 alternate/selective bootstrap the selection between the alternate and selective bootstrap modes is done by comparing two signatures to predefined user and alternate signatures. 1 1 user code the st10f27x starts fetching code form internal rom or external rom according to ea pin?s level.
AN2168 5 boot management 11/15 figure 7. st10f27x standard bootstrap via can 5.2 single chip mode if the bootstrap mode isn?t activated (p0l.4 =1 & p0l.5=1) and ea = 1 during reset, the single ship mode is enabled. in this mode, the reset vector is located in the internal memory. in this case, the internal flash must contain a valid program at address 00?0000. 5.3 boot from external memories if the bootstrap mode isn?t activated (p0l.4 =1 & p0l.5=1) and ea = 0, the st10f27x will start fetching code from the external memory at address 00?0000. in this mode, the internal flash can not be accessed. p0l.4 = 0 st10f27x p0l.5 = 0 vdd 8 kohms p4.5 : can1_rx vdd external device vss
6 st10f27x basic schematics AN2168 12/15 6 st10f27x basic schematics the schematic shown in figure 8 illustrates the minimum hardwa re requirements to get the st10f276 running. in this example: the st10f276 runs at 40mhz generated using an 8-mhz external crystal and a prescaler equal to 5 ( p0h.7 = 1, p0h.6 = p0h.5 = 0 during reset). please refer to the section 2: clock management on page 4 . the schematic shows the st10 in stand-alone mode, without any external memory. the standard bootstrap mode is activated by plugging the jumper j1 (p0l.4 = 0). as there is no external memory, the device will al ways boot from inte rnal memory and ea can be forced to high level through the stand by mode ram battery. rs232 comminication with a host is estab lished using the stmicroelectronics st3232 transciever. please refer to its related datasheet for detailed specification.
AN2168 6 st10f27x basic schematics 13/15 figure 8. st10f27 basic schematic 1 2 3 4 5 6 a b c d 6 5 4 3 2 1 d c b a t i t l e n u m b e r r e v i s i o n s i z e b d a t e : 2 8 - j u n - 2 0 0 5 s h e e t o f f i l e : v d d 1 7 v s s 1 8 v a r e f 3 7 v a g n d 3 8 v s s 4 5 v d d 4 6 v s s 5 5 v 1 8 5 6 v s s 7 1 v d d 7 2 v s s 8 3 p 3 . 1 0 / t x d 0 7 7 r p d 8 4 v d d 8 2 p 3 . 1 1 / r x d 0 7 8 v d d 9 3 v s s 9 4 e a / v s t b y 9 9 p 0 l . 0 1 0 0 p 0 l . 1 1 0 1 p 0 l . 2 1 0 2 p 0 l . 3 1 0 3 p 0 l . 4 1 0 4 p 0 l . 5 1 0 5 p 0 l . 6 1 0 6 p 0 l . 7 1 0 7 p 0 h . 0 1 0 8 p 0 h . 4 1 1 4 p 0 h . 5 1 1 5 p 0 h . 6 1 1 6 p 0 h . 7 1 1 7 p 0 h . 3 1 1 3 v d d 1 2 6 v s s 1 2 7 v d d 1 3 6 x t a l 2 1 3 7 x t a l 1 1 3 8 p 0 h . 2 1 1 2 v s s 1 1 0 p 0 h . 1 1 1 1 v s s 1 3 9 r s t i n 1 4 0 v d d 1 0 9 s t 1 0 f 2 7 6 1 0 0 n 1 0 0 n 4 . 7 k 4 x 8 k 1 m 2 2 0 k h a r d w a r e r e s e t 5 v 8 m h z 5 v v d d _ 1 v d d _ 2 v s s _ 1 v s s _ 2 v s s _ 3 v d d _ 3 8 k v s s _ 4 v d d _ 4 v s s _ 5 v d d _ 5 v d d _ 6 v s s _ 6 v d d _ 7 v s s _ 7 v a r e f a g n d v s s _ 8 v d d _ 8 c 1 + + 1 c 1 - - 3 c 2 + 4 c 2 - 5 t 1 i n 1 1 t 2 i n 1 0 r 1 o u t 1 2 r 2 o u t 9 v + 2 v - 6 t 1 o u t 1 4 t 2 o u t 7 r 1 i n 1 3 r 2 i n 8 v d d 1 6 g n d 1 5 s t 3 2 3 2 1 0 0 n 1 0 0 n 1 0 0 n 1 0 0 n 1 6 2 7 3 8 4 9 5 5 v r s 2 3 2 c o n n e c t o r + 1 u f + 1 u f 1 0 0 n 1 2 j 1 5 1 0 0 n 1 0 0 n 1 0 0 n 1 0 0 n 1 0 0 n 1 0 0 n 1 0 0 n 1 0 0 n
7 revision history AN2168 14/15 7 revision history date revision changes 14-sep-2006 1 initial release 27-feb-2007 2 references to cancelled application note removed 24-sep-2013 3 updated disclaimer.
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